What are Top Down and Bottom Up compile methodologies in Synthesis?
In top down compile methodology you start compiling from the top of the design hierarchy. Whereas in the bottom up compile methodology we start building from the bottom of the design hierarcy. In general we go for the top down compile method.
Why should we not use tri-state logic arbitrarily?
Tri-state logic reduces testability
Tri-state logic is difficult to optimize - since it cannot be buffered leading to max fanout violations and heavily loaded nets
However tri-state logic can provide significant savings in area.
Monday, December 31, 2007
Sunday, December 30, 2007
Guidelines
THINK HARDWARE while coding RTL
Keep related combo logic in the same module
Isolate state machines from other logic
Isolate clock syncronizers into separate blocks
Behavioral level coding abstraction allows the design to be independent of timing and explicit sequencing
Avoid multiple clocks per block
Put all the clock related logic in a block
See that you dont have any logic at the top level and instead make it a list of instantiations
Module name same as file name
only one module per file
Register all outputs wherever possible
Implement next state combo using a case statement
Latches make DFT Scan insertion difficult if not impossible and also makes STA no easy.
To avoid latches: -
Avoid full case and parallel case directives as much as possible
Multiple if statements result in the creation of a priority encoder structure
Keep related combo logic in the same module
Isolate state machines from other logic
Isolate clock syncronizers into separate blocks
Behavioral level coding abstraction allows the design to be independent of timing and explicit sequencing
Avoid multiple clocks per block
Put all the clock related logic in a block
See that you dont have any logic at the top level and instead make it a list of instantiations
Module name same as file name
only one module per file
Register all outputs wherever possible
Implement next state combo using a case statement
Latches make DFT Scan insertion difficult if not impossible and also makes STA no easy.
To avoid latches: -
- Assign a value to the output in every branch of a case statement
- All if's and/or elseif's should end with an else
Avoid full case and parallel case directives as much as possible
Multiple if statements result in the creation of a priority encoder structure
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