Static Timing Analysis - Prime Time

How many minimum modes i should qualify STA for a chip
1. Scan Shift mode
2. Scan Capture mode
3. MBIST mode
4. Functional modes for Each Interface
5. Boundary scan mode
6. scan-compression mode

How many minimum process lots , should STA be qualified.

1. Fast corner
2. Slow corner
3. Typical corner
How many minimum Timing , Should STA be qualified.

1. normal delay mode(with out applying deration)
2. On-chip variation mode (deration applied)
3. SI mode (Signal integrity cross talk impact on STA)
How many minimum STA runs should we needed to address = 6*3*3.

A Typical RC script for Scan Insertion

read_netlist -top ahb_master

read_sdc ahb_master.sdc

set_attribute dft_scan_style muxed_scan

define_dft test_mode -name test_mode -active high test_mode

define_dft shift_enable -name scan_en -hookup_pin [find / -pin dft_fix/Z] -active high ahb_master/dft_fix/Z (if using an internal pin for scan enable)

define_dft scan_chain -name chain1 -sdi -sdo -shared_out -shared_select test_mode

(assuming that you are using shared scan input and scan outputs)

check_dft_rules

report dft_registers > dft_reg.rpt

report dft_setup > dft_setup.rpt

set_attribute dft_max_length_of_scan_chains

synthesize -to_mapped

connect_scan_chains -preview -auto_create_chains

connect_scan_chains -pack

report dft_chains > chain.rpt

write_hdl >

write_script > dft.tcl

write_atpg -mentor

I have found that the RC tool does not write out a really useful testproc file
I will soon upload a proc file, keep watching

DFT Adviosr typical do file

analyze control signals -auto_fix

set system mode dft
setup scan identification full_scan

setup test_point identification -control 0 -observe 0 -noverbose
run
report statistics
report sequential instances -unidentified -nonscannable
write scan identification seq_inst_rpt -replace -identified -defined_scan
insert test logic -scan on -test_point on -ram on -number 1 -hierarchical off
write netlist -replace
write atpg setup -replace

Please Note

Take care while using the dont_touch attribute when there are gated clocks in the design

Good Question

What are Top Down and Bottom Up compile methodologies in Synthesis?

In top down compile methodology you start compiling from the top of the design hierarchy. Whereas in the bottom up compile methodology we start building from the bottom of the design hierarcy. In general we go for the top down compile method.

Why should we not use tri-state logic arbitrarily?

Tri-state logic reduces testability
Tri-state logic is difficult to optimize - since it cannot be buffered leading to max fanout violations and heavily loaded nets

However tri-state logic can provide significant savings in area.

To Do

Look for Synopsys application notes on coding guidelines

Guidelines

THINK HARDWARE while coding RTL

Keep related combo logic in the same module

Isolate state machines from other logic

Isolate clock syncronizers into separate blocks

Behavioral level coding abstraction allows the design to be independent of timing and explicit sequencing

Avoid multiple clocks per block

Put all the clock related logic in a block

See that you dont have any logic at the top level and instead make it a list of instantiations

Module name same as file name

only one module per file

Register all outputs wherever possible

Implement next state combo using a case statement

Latches make DFT Scan insertion difficult if not impossible and also makes STA no easy.

To avoid latches: -

1. Assign a value to the output in every branch of a case statement
2. All if's and/or elseif's should end with an else

To implement muxes, use case statements exclusively.

Avoid full case and parallel case directives as much as possible

Multiple if statements result in the creation of a priority encoder structure